Nvidia Expands CUDA Platform Support to RISC-V Architecture

Nvidia has announced at the 2025 RISC-V Summit in China that its CUDA software platform will now support the RISC-V instruction set architecture (ISA) for CPU integration. This marks a significant development in enabling RISC-V CPUs for performance-intensive applications, traditionally dominated by x86 or ARM processors. While it is unlikely that RISC-V will replace established processors in hyperscale data centers in the immediate future, it is seen as a promising option for edge devices, such as Nvidia’s Jetson modules. RISC-V’s inclusion in the CUDA ecosystem signals Nvidia’s vision to integrate this open-source architecture into its heterogeneous compute platforms. The integration will allow RISC-V CPUs to manage tasks like system drivers, application logic, and OS functions, while GPUs take care of parallel workloads. Additionally, a DPU is expected to handle networking, forming a complete system of CPU orchestration, GPU compute, and data movement. This expansion could help Nvidia maintain the relevance of CUDA in the Chinese market, despite geopolitical tensions affecting the availability of its high-end chips. The shift to RISC-V could also offer greater flexibility in terms of CPU design, making it a competitive choice for future compute architectures.