Cadence Introduces Efficient AI Co-Processor to Address Non-Matrix Tasks

The article discusses the evolving landscape of AI chip design, particularly the growing need for specialized co-processors to handle scalar and vector operations that traditional AI accelerators like NPUs aren’t optimized for. While most AI chips focus on matrix operations crucial for neural networks, many tasks such as activations and averaging still rely on general-purpose CPUs or DSPs, which often include unnecessary features. To address this inefficiency, Cadence Design has launched the Tensilica NeuroEdge AI Co-Processor. Derived from its Vision DSP platform, the NeuroEdge delivers similar performance to standard DSPs but uses 30% less chip area, making it more cost- and energy-efficient. It is fully supported by Cadence’s existing software stack and is scalable to fit various applications. The chip supports multiple data formats and integrates smoothly with other SoC components via standard or high-bandwidth interfaces. Cadence envisions strong use cases for NeuroEdge in sectors like automotive, robotics, healthcare, and edge AI, especially where ISO 26262 safety certification is required. This innovation provides a more tailored and efficient solution for offloading AI tasks not suited for matrix operations, helping companies bring their custom AI hardware to market faster.